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? 2007 california micro devices corp. all rights reserved. 12/17/07 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 1 CM1231 CM1231 issue x-1 two-channel picoguard xp tm esd clamp protection array features ? two channels of esd protection ? exceeds esd protection to iec61000-4-2 level 4: ? 12kv contact discharge (out pins) ? two-stage matched clamp architecture ? matching-of-series resistor (r) of 10m typical ? flow-through routing for high-speed signal integrity ? differential channel input capacitance matching of 0.02pf typical. ? improved powered asic latchup protection ? dramatic improvement in esd protection vs. best in class single-stage diode arrays ? 40% reduction in peak clamping voltage ? 40% reduction in peak residual current ? withstands over 1000 esd strikes* ? available in a sot23-6 package applications ? usb devices data port protection ? general high-speed data line esd protection product description the CM1231 is a member of the xtremeesd tm product family and is specifically designed for next generation deep submicron asic protection. these devices are ideal for protecting systems with high data and clock rates and for circuits requiring low capacitive loading such as usb 2.0. the CM1231 incorporates the picoguard xp tm dual stage esd architecture which offers dramatically higher system level esd protection compared with traditional single clamp de signs. in addition, the CM1231 provides a controlled filter roll-off for even greater spurious emi suppression and signal integrity. the CM1231 protects against esd pulses up to 12kv contact on the ?out? pins per the iec 61000-4-2 standard. the device also features easily routed "pass-through" differential pinouts in a 6-lead sot23 package. * standard test condition is iec61000-4-2 level 4 test circuit with each (a out /b out ) pin subjected to 12kv contact discharge for 1000 pulses. discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. electrical schematic v p v n ground rail CM1231 circuitry under protection positive supply rail v cc 1 1 a in a out b in b out v p v n connector
? 2007 california micro devices corp. all rights reserved. 2 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 12/17/07 CM1231 issue x-1 single and dual clamp esd protec- tion the following sections describe the standard single clamp esd protection device and the dual clamp esd protection architecture of the CM1231. single clamp esd protection conceptually, an esd protection device performs the following actions upon a strike of esd discharge into the protected asic (see figure 1 ). 1. when an esd potential is applied to the system under test (contact or air-discharge), kirchoff?s current law (kcl) dictates that the electrical overstress (eos) currents will immediately divide throughout the circuit, based on the dynamic impedance of each path. 2. ideally, the classic shunt esd clamp will switch within 1ns to a low-impedance path and return the majority of the eos current to the chassis shield/ reference ground. in actuality, if the esd compo- nent's response time (t clamp ) is slower than the asic it is protecting, or if the dynamic resistance (r dyn ) is not significantly lower than the asic's i/o cell circuitry, then the asic will have to absorb a large amount of the eos energy, and may be more likely to fail. 3. subsequent to the esd/eos event, both devices must immediately return to their original specifica- tions, ready for an additional strike. any deteriora- tion in parasitics or cl amping capabilit y should be considered a failure, as it can affect signal integrity or subsequent protection capability (this is known as "multi-strike" capability.) figure 1. single clamp esd protection block diagram dual clamp esd protection in the CM1231 dual clamp picoguard xp tm architecture, the first stage begins clamping immediately, as it does in the single clamp case. the dramatically reduced i res current from stage one passes through the 1 series element and then gradually feeds into the stage two esd device (see figure 2 ). the series inductive and resistive elements further limit the current in to the second stage, and greatly attenuate the resultant peak incident pulse presented at the asic side of the device. this disconnection between the outside node and the inside asic node allows the stage one clamps to turn on and remain in the shunt mode before the asic begins to shunt the reduced residual pulse. this gives the advantage to the esd component in the current division equation, and dramatically reduces the residual energy that the asic must dissipate. figure 2. dual clamp esd protection block diagram connector i/o esd protection device asic esd protection device esd strike i residual i shunt asic dut asic esd protection stage 1 i shunt1 esd protection stage 2 i shunt2 i residual i/o connector esd strike 1
? 2007 california micro devices corp. all rights reserved. 12/17/07 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 3 CM1231 CM1231 issue x-1 CM1231 architecture overview the picoguard xp tm two-stage per channel matched clamp architecture with isolated clamp rails features a series element to radically reduce the residual esd current (i res ) that enters the asic under protection (see figure 3 ). from stage 1 to stage 2, the signal lines go through matched dual 1 resistors. the function of the series element (dual 1 resistors for the CM1231) is to optimize the operation of the stage two diodes to reduce the final i res current to a minimum while maintaining an acceptable insertion impedance that is negligible for the associated signaling levels. each stage consists of a traditional low-cap dual rail clamp structure which steer the positive or negative esd current pulse to either the positive (v p ) or negative (v n ) supply rail. a zener diode is embedded between v p and v n , offering two advantages. first, it protects the v cc rail against esd strikes. second, it eliminates the need for an additional bypass capacitor to shunt the positive esd strikes to ground. the CM1231 therefore replaces as many as 7 discrete components, while taking advantage of precision internal component matching for improved signal integrity, which is not othe rwise possible with discrete components at the system level. figure 3. CM1231 block diagram (i esd flow during a positive strike) advantages of the CM1231 dual stage esd protection architecture figure 4 illustrates a single stage esd protection device. the inductor element represents the parasitic inductance arising from the bond wire and the pcb trace leading to the esd protection diodes. figure 4. single stage esd protection model figure 5 illustrates one of the two CM1231 channels. similarly, the inductor elements represent the parasitic inductance arising from the bond wire and pcb traces leading to the esd protection diodes as well. figure 5. CM1231 dual stage esd protection model v cc v p v n positive supply rail ground rail i residual i esd 1 circuitry under protection esd stage bond wire inductance asic connector bond wire inductance asic connector series element 1 st stage 2 nd stage bond wire inductance
? 2007 california micro devices corp. all rights reserved. 4 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 12/17/07 CM1231 issue x-1 CM1231 inductor elements in the CM1231 dual stage picoguard xp tm architecture, the inductor elements and esd protection diodes interact differently compared to the single stage model. in the single stage model, the inductive element presents high impedance at high frequency, i.e. during an esd strike. the impedance increases the resistance of the conduction path leading to the esd protection element. this limits the speed that the esd pulse can discharge through the single stage protection element. in the picoguard xp tm architecture, the inductance elements are in series to the conduction path leading to the protected device. the elements actually help to limit the current and voltage striking the protected device. the reactance of the series and the inductor elements in the second stage forces more of the esd strike current to be shunted through the first stage. at the same time the voltage drop across series element helps to lower the clamping voltage at the protected terminal. the inductor elements also tune the impedance of the stage by cancelling the capa citive load presented by the esd diodes to the signal line. this improves the signal integrity and makes the esd protection stages more transparent to the high bandwidth data signals passing through the channel. the innovative picoguard xp architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the esd current strike to the protected device and also improves the signal integrity of the system by balancing the capacitive loading effects of the esd diodes. graphical comparison and test setup the following graphs (see figure 6 , figure 7 , and figure 8 ) show that the CM1231 (dual stage esd protector) low- ers the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a standard single stage device. this data was derived using the test setups shown in figure 9 and figure 10 . figure 6. iec 61000-4-2 vpeak vs. loading (rdup*) figure 7. iec 61000-4-2 vclamp vs. loading (rdup*) * rdup indicates the amount of resistance (load) supplied to the device under protection (dup) through a vari- able resistor. normalized vpeak 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 25 rdup ( ) voltage single stage esd device CM1231 normalized vclamp initial (0-50ns) 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 25 voltage single stage esd device CM1231 rdup ( )
? 2007 california micro devices corp. all rights reserved. 12/17/07 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 5 CM1231 CM1231 issue x-1 figure 8. iec 61000-4-2 i res (residual esd peak current) vs. loading (rdup) figure 9. single stage esd device test setup figure 10. CM1231 test setup i res 0 2 4 6 8 10 12 0 5 10 15 20 25 rdup ( ) current (a) single stage esd device cm 1231 voltage probe current probe single stage esd device i residual iec 6100-4-2 test standards r variable device under protection (dup) voltage probe current probe CM1231 i residual iec 6100-4-2 test standards r variable device under protection (dup)
? 2007 california micro devices corp. all rights reserved. 6 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 12/17/07 CM1231 issue x-1 ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. specifications note 1: exposure to absolute maximum rating conditions for extended periods may affect device reliability. package / pinout diagrams note: 1) this drawing is not to scale. 13 1 2 64 d312 5 v p b in b out a out v n a in pin descriptions pin pin name pin description notes 1a out bidirectional clamp to connector (outside the system) 2v n ground return to shield 3a in bidirectional clamp to asic (inside the system) 4b in bidirectional clamp to asic (inside the system) 5v p bias voltage (optional) 6b out bidirectional clamp to connector (outside the system) part numbering information pin pac kag e lead-free finish part marking 6 sot23-6 CM1231-02so d312 absolute maximum ratings parameter rating units operating supply voltage (v p )6.0v diode forward dc current (a out /b out side) 8.0 ma continuous current through signal pins (in to out) 1000 hours 125 ma operating temperature range -40 to +85 c storage temperature range -65 to +150 c dc voltage at any channel input (v n - 0.5) to (v p + 0.5) v package power rating (sot23-6) 225 mw
? 2007 california micro devices corp. all rights reserved. 12/17/07 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 7 CM1231 CM1231 issue x-1 note 1: all parameters specified at t a = ?40c to +85c unless otherwise noted. note 2: this parameter is guaranteed by des ign and verified by device characterization note 3: capacitance measured from out to v n with in floating. electrical operating characteristics (see note 1) symbol parameter conditions min typ max units v p operating supply voltage 5 5.5 v i cc5 operating supply current v p = 5v 1 a v f diode forward voltage top diode bottom diode i f = 8ma, t a = 25c; note 2 0.60 0.60 0.80 0.80 0.95 0.95 v v v esd esd protection, contact discharge per iec 61000-4-2 standard out-to- v n contact in-to- v n contact t a = 25c; note 2 12 4 kv kv i res residual esd peak current on rdup (resistance of device under protection) iec 61000-4-2 8kv; rdup = 5 , t a = 25c; note 2 2.3 a v cl channel clamp voltage positive transients negative transients i pp = 1a, t a = 25c, t p = 8/20s, zap at out, measure at in; note 2 +9 ?1.4 v v r dyn dynamic resistance positive transients negative transients i pp = 1a, t a = 25c, t p = 8/20s, zap at out, measure at in; note 2 0.4 0.3 c out out capacitance f=1 mhz, v p =5.0v, v in =2.5v, v osc =30mv; note 2, 3 1.5 pf c out channel to channel capacitance match f=1 mhz, v p =5.0v, v in =2.5v, v osc =30mv note 2 0.02 pf r s series resistance note 2 1 r s channel to channel resistance match note 2 10 30 m
? 2007 california micro devices corp. all rights reserved. 8 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 12/17/07 CM1231 issue x-1 performance information figure 11. clamping voltage vs. peak current figure 12. capacitance vs. bias voltage typical filter performance (nominal conditions unless specified otherwise, 0v dc bias, 50 environment) figure 13. typical single-ended s2 1 plot (1db/div, 3mhz to 6ghz) clamping voltage vs . peak current 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 12345 iec61000-4-5 8/20us peak current (a) clamping voltage (v) zap at out; measure at out zap at out; measure at in out-to-vn capacitance, in floating, vp=5v 0.0 0.5 1.0 1.5 2.0 2.5 012345 bias voltage (v) capacitance (pf) out-to-v n capacitance, in floating, v p =5v 0 db -1 db -2 db -3 db 3 10 100 1000 2000 6000 frequency (mhz) -4 db -5 db -6 db -7 db -8 db -9 db -1 0 db
? 2007 california micro devices corp. all rights reserved. 12/17/07 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 9 CM1231 CM1231 issue x-1 CM1231 application and guidelines the CM1231 has an integrated zener diode between v p and v n (for each of the two stages). this greatly reduces the effect of supply rail inductance l 2 on v cl by clamping v p at the breakdown voltage of the zener diode. however, for the lowest possible v cl , especially when v p is biased at a voltage significantly below the zener breakdown voltage, it is recommended that a 0.22 f ceramic chip capacitor be connected between v p and the ground plane. with the CM1231, this additional bypass capacitor is generally not required. as a general rule, the esd protection array should be located as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply, ground planes and between the signal input and the esd device to minimize stray series inductance. figure 14. typical layout with optional v p cap footprint additional information see also california micro devices application note ap-209 , ?design considerations for esd protection,? in the applications section at www.calmicro.com .
? 2007 california micro devices corp. all rights reserved. 10 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 12/17/07 CM1231 issue x-1 mechanical details sot23-6 mechanical specifications, 6 pin the CM1231 is supplied in a 6-pin sot23 package. dimensions are presented below. dimensions for sot23-6 package package dimensions package sot23-6 jedec no. mo-178 (var. ab) pins/leads 6 dimensions millimeters inches min max min max a -- 1.45 -- 0.0571 a1 0.00 0.15 0.0000 0.0059 b 0.30 0.50 0.0118 0.0197 c 0.08 0.22 0.0031 0.0087 d 2.75 3.05 0.1083 0.1201 e 2.60 3.00 0.1024 0.1181 e1 1.45 1.75 0.0571 0.0689 e 0.95 bsc 0.0374 bsc e1 1.90 bsc 0.0748 bsc l 0.30 0.60 0.0118 0.0236 l1 0.60 ref 0.0236ref # per tape and reel 3000 pieces controlling dimension: millimeters mechanical package diagrams top view a side view d a1 l1 end view c l 12 3 65 4 e1 e e1 e b pin 1 marking
? 2007 california micro devices corp. all rights reserved. 12/17/07 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 11 CM1231 CM1231 issue x-1 tape and reel specifications figure 15. tape and reel specifications part nu mbe r package size (mm) pocket size (mm) b 0 x a 0 x k 0 tape width w reel diameter qty per reel p 0 p 1 CM1231 3.05 x 3.00 x 1.45 3.20 x 3.20 x 1.40 8mm 178mm (7") 3000 4mm 4mm to p for tape feeder reference cover tape p 1 only including draft. concentric around b. k o embossment user direction of feed 0.2 mm p o center lines of cavity w 10 pitches cumulative tolerance on tape a o b o

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